Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes
AT91SAM9M10-G45-EK
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SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
 
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and
stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected
at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter,
i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism 
only
, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resyn-
chronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the
receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter
is operating with one stop bit.
 illustrate start detection and character reception when USART operates in asyn-
chronous mode.
Figure  31-12.
Asynchronous Start Detection 
Figure  31-13.
Asynchronous Character Reception
Sampling
Clock (x16)
RXD
Start 
Detection
Sampling
Baud Rate
Clock
RXD
Start 
Rejection
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
0
1
2
3
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
D0
Sampling
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start 
Detection
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples
16 
samples