Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes
AT91SAM9M10-G45-EK
Page of 1361
 523
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
 
• RSTSTA:  Reset  Status  Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE, LINSNRE  and RXBRK in
US_CSR.
• STTBRK:  Start  Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted. 
• STPBRK:  Stop  Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO:  Start  Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA:  Send  Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. 
• RSTIT:  Reset  Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK:  Reset  Non  Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO:  Rearm  Time-out
0: No effect
1: Restart Time-out
• RTSEN/FCS:  Request  to  Send  Enable/Force  SPI  Chip  Select
– If USART does not operate in SPI Master Mode (USART_MODE 
≠ 0xE):
0: No effect.
1: Drives the pin RTS to 0.
– If USART operates in SPI Master Mode (USART_MODE = 0xE):
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
devices supporting the CSAAT Mode (Chip Select Active After Transfer).