Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Master Read with Multiple Data Bytes

The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.

When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or
write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
When performing read operations with an internal address, the TWI performs a write operation to set the internal
address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after
sending the IADR) is sometimes called “repeated start” (Sr) in I

2

The three internal address bytes are configurable through the Master Mode register (TWI_MMR).

If the slave device supports only a 7-bit address, i.e. no internal address, 

 must be set to 0.

In the figures below the following abbreviations are used:

N

A

S

DADR

R

DATA n

A

A

DATA (n+1)

A

DATA (n+m)

DATA (n+m)-1

P

TWD

TXCOMP

Write START Bit

RXRDY

Write STOP Bit

after next-to-last data read

Read RHR

DATA n

Read RHR

DATA (n+1)

Read RHR

DATA (n+m)-1

Read RHR

DATA (n+m)

• S

Start

• Sr

Repeated Start

• P

Stop

• W

Write

• R

Read

• A

Acknowledge

• N

Not Acknowledge

• DADR

Device Address

• IADR

Internal Address