Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
738
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
36.5
Programming Interface
36.5.1
Initialization
36.5.1.1
Configuration
Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit
and receive circuits are disabled. See the description of the network control register and network configuration reg-
ister earlier in this document.
and receive circuits are disabled. See the description of the network control register and network configuration reg-
ister earlier in this document.
To change loop-back mode, the following sequence of operations must
be followed:
1.
Write to network control register to disable transmit and receive circuits.
2.
Write to network control register to change loop-back mode.
3.
Write to network control register to re-enable transmit or receive circuits.
Note:
These writes to network control register cannot be combined in any way.
36.5.1.2
Receive Buffer List
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data
structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor
entries as defined in
structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor
entries as defined in
. It points to this data structure.
Figure 36-2.
Receive Buffer List
To create the list of buffers:
1.
Allocate a number (
n
) of buffers of 128 bytes in system memory.
2.
Allocate an area 2
n
words for the receive buffer descriptor entry in system memory and create
n
entries in
this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0.
3.
If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0
set to 1).
set to 1).
4.
Write address of receive buffer descriptor entry to EMAC register
receive_buffer
queue pointer.
5.
The receive circuits can then be enabled by writing to the address recognition registers and then to the
network control register.
network control register.
Receive Buffer Queue Pointer
(MAC Register)
Receive Buffer 0
Receive Buffer 1
Receive Buffer N
Receive Buffer Descriptor List
(In memory)
(In memory)