Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 746

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For con-
formance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations)

Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this
bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters
decrement time from 512 bit times, to every 

rx_clk

cycle.

When set, transmission pauses when a valid pause frame is received.

Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.

When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in
bytes 13 and 14 — length/type ID 

= 0600 — are not be counted as length errors.

When set, the FCS field of received frames are not be copied to memory.

Enable Frames to be received in half-duplex mode while transmitting.

When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this
bit must be set to 0.

00

MCK divided by 8 (MCK up to 20 MHz)

01

MCK divided by 16 (MCK up to 40 MHz)

10

MCK divided by 32 (MCK up to 80 MHz)

11

MCK divided by 64 (MCK up to 160 MHz)

00

No offset from start of receive buffer 

01

One-byte offset from start of receive buffer

10

Two-byte offset from start of receive buffer

11

Three-byte offset from start of receive buffer