Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 797

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register.
Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register.

To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped.

 

To do so,

INTDIS_DMA and TX_BK_RDY may be set in the UDPHS_EPTCTLENBx register.

 

It is also possible for the appli-

cation to wait for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor
UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1.

Then the application can chain a new transfer descriptor.

The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be
used to stop DMA transfers in case of errors. 

The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx
register).

Data IN Transfer for Endpoint with One Bank 

USB Bus 
Packets

FIFO
Content

TX_COMPLT Flag
(UDPHS_EPTSTAx) 

TX_PK_RDY 
Flag
(UDPHS_EPTSTAx)

Prevous Data IN TX

Microcontroller Loads Data in FIFO

Data is Sent on USB Bus

Interrupt Pending

Set by firmware

Cleared by hardware

Set by the firmware

Cleared by hardware

Interrupt Pending

Cleared by firmware

DPR access by firmware

DPR access by hardware

Cleared by firmware

Payload in FIFO

Set by hardware

Data IN 2

Token IN

NAK

ACK

Data IN 1

Token IN

Token IN

ACK

Data IN 1

Load in progress

Data IN 2