Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be pro-
grammed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is
used. The different transfer types are shown in 

.

The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx,
DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are
enabled.

1.

Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a free (disabled) 
channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt sta-
tus register, DMAC_EBCISR.

3.

Program the following channel registers:

a.

Write the starting source address in the DMAC_SADDRx register for channel x.

b.

Write the starting destination address in the DMAC_DADDRx register for channel x.

c.

fields set to one and AUTO field set to 0.

d.

Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx regis-
ters for channel x. For example, in the register, you can program the following:

– i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow 

control device by programming the FC of the DMAC_CTRLBx register.

– ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_WIDTH field.

– Transfer width for the destination in the DST_WIDTH field.

– Source AHB Master interface layer in the SIF field where source resides.

– Destination AHB Master Interface layer in the DIF field where destination resides.

– Incrementing/decrementing or fixed address for source in SRC_INC field.

– Incrementing/decrementing or fixed address for destination in DST_INC field.

e.

Write the channel configuration information into the DMAC_CFGx register for channel x.

– i. Designate the handshaking interface type (hardware or software) for the source and destination 

peripherals. This is not required for memory. This step requires programming the 
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking 
interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking 
interface to handle source/destination requests.

– ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a 

handshaking interface to the source and destination peripheral. This requires programming the 
SRC_PER and DST_PER bits, respectively.