Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
948
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
4.
Write the channel configuration information into the DMAC_CFGx register for channel x.
a.
Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking inter-
face to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software
handshaking interface source/destination requests.
peripherals. This is not required for memory. This step requires programming the
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking inter-
face to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software
handshaking interface source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination peripheral, assign
handshaking interface to the source and destination peripheral. This requires programming the
SRC_PER and DST_PER bits, respectively.
handshaking interface to the source and destination peripheral. This requires programming the
SRC_PER and DST_PER bits, respectively.
5.
Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last) are set as
shown in Row 6 of
shown in Row 6 of
item must be set as described in Row 1 of
.
shows a Linked List
example with two list items.
6.
Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-
zero and point to the next Linked List Item.
zero and point to the next Linked List Item.
7.
Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to the start destina-
tion buffer address proceeding that LLI fetch.
tion buffer address proceeding that LLI fetch.
8.
Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in
memory is cleared.
memory is cleared.
9.
If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx reg-
ister for channel x.
ister for channel x.
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx
register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the
DMAC_EBCISR register.
.
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n is the channel
number. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx regis-
ters are fetched. The LLI.DMAC_SADDRx register although fetched is not used.
ters are fetched. The LLI.DMAC_SADDRx register although fetched is not used.
16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data
(assuming non-memory peripherals). DMAC acknowledges at the completion of every transaction (chunk
and single) in the buffer and carry out the buffer transfer.
and single) in the buffer and carry out the buffer transfer.
17. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx register is written out
to the same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is
the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
transfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The
LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion Therefore, software can poll the
LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer
transfer has completed.
the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
transfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The
LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion Therefore, software can poll the
LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer
transfer has completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the LLI.DMAC_CTRLAx.DONE bit
in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has com-
pleted. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer.
in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has com-
pleted. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer.
18. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets the buffer complete
interrupt. The DMAC samples the row number as shown in
Row 1, then the DMAC transfer has completed. Hardware sets the transfer complete interrupt and dis-
ables the channel. You can either respond to the Buffer Complete or Chained buffer Transfer Complete
ables the channel. You can either respond to the Buffer Complete or Chained buffer Transfer Complete