Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
951
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface master layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
e.
If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx
register for channel x.
register for channel x.
f.
If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx regis-
ter for channel x.
ter for channel x.
g.
Write the channel configuration information into the DMAC_CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking
interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the
software handshaking interface to handle source/destination requests.
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking
interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the
software handshaking interface to handle source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign
handshaking interface to the source and destination peripheral. This requires programming the
SRC_PER and DST_PER bits, respectively.
SRC_PER and DST_PER bits, respectively.
4.
After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0 of the
DMAC_EN.ENABLE register is enabled.
DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0 of the
DMAC_EN.ENABLE register is enabled.
5.
Source and destination request single and chunk DMAC transactions to transfer the buffer of data
(assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction
(chunk and single) in the buffer and carries out the buffer transfer.
(assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction
(chunk and single) in the buffer and carries out the buffer transfer.
6.
When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The
DMAC_DADDRx register remains unchanged. Hardware sets the buffer complete interrupt. The DMAC
then samples the row number as shown in
DMAC_DADDRx register remains unchanged. Hardware sets the buffer complete interrupt. The DMAC
then samples the row number as shown in
. If the DMAC is in Row 1, then the
DMAC transfer has completed. Hardware sets the transfer complete interrupt and disables the channel.
So you can either respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE
field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by hardware, to
detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
So you can either respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE
field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by hardware, to
detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
7.
The DMAC transfer proceeds as follows:
a.
If the buffer complete interrupt is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then
stalls until STALLED[n] bit of DMAC_CHSR is cleared by writing in the KEEPON[n] field of
DMAC_CHER register where n is the channel number. If the next buffer is to be the last buffer in the
DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic
mode bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in
number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then
stalls until STALLED[n] bit of DMAC_CHSR is cleared by writing in the KEEPON[n] field of
DMAC_CHER register where n is the channel number. If the next buffer is to be the last buffer in the
DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic
mode bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in
. If the next buffer is not the last buffer in the DMAC transfer then the automatic transfer mode bit
b.
If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel num-
ber) then hardware does not stall until it detects a write to the buffer transfer completed interrupt
enable register but starts the next buffer transfer immediately. In this case software must clear the
automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
ber) then hardware does not stall until it detects a write to the buffer transfer completed interrupt
enable register but starts the next buffer transfer immediately. In this case software must clear the
automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
before the last buffer of the DMAC transfer has completed.
.