Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 955

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the 
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that 
described in Row 1 of 

was the last buffer in the DMAC transfer. 

The DMAC transfer might look like that shown in 

 Note that the destination address is

decrementing.

DMAC Transfer with Linked List Source Address and Contiguous Destination Address

The DMAC transfer flow is shown in 

SADDR(2)

SADDR(1)

SADDR(0)

DADDR(2)

DADDR(1)

DADDR(0)

Buffer 2

Buffer 1

Buffer 0

Buffer 0

Buffer 1

Buffer 2

Address of 

Source Layer

Address of

Destination Layer

Source Buffers

Destination Buffers