Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer 
web site to check current device availability.



Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Assignment Register 
(CCFG_EBICSA) in the Bus Matrix. 



Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.

The DDR2 initialization sequence is described in the subsection “DDR2 Device Initialization” of the DDRSDRC section.

In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data 
bus. NFD0_ON_D16 is to be set to 1.