Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

Reset value is “0”.

This field is unique to Low-power SDRAM. It selects the driver strength of SDRAM output.

After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and DS bits 
are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a 
pending read or write access.

Reset value is “00”.

This field defines when low-power mode is enabled. 

Reset value is “1”.

This mode is unique to DDR2-SDRAM devices. This mode allows to determine the active power-down mode, which determines 
performance versus power saving.

0 = Fast Exit 

1 = Slow Exit 

After the initialization sequence, as soon as APDE field is modified Extended Mode Register, located in the memory of the exter-
nal device, is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done before entering 
in self refresh mode or during a refresh command and a pending read or write access

Reset value is “0”.

This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is 
function of DDRSDRC integration in a system. DDRSDRC can either share or not share an external bus with another controller.

00

The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. 

01

The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.

10

The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.

11

Reserved

00

Update is disabled.

01

DDRSDRC shares external bus. Automatic update is done during a refresh command and a pending read or write 
access in SDRAM device.

10

DDRSDRC does not share external bus. Automatic update is done before entering in self refresh mode.

11

Reserved