Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
![Atmel](https://files.manualsbrain.com/attachments/0369829915bda09f9c2e00fb805a7753579683b5/common/fit/150/50/8d2bf08978ec3e5bc63f4343ac5e91ce8d0e40045619fa520d910d64af8f/brand_logo.png)
Product codes
ATSAM4L-EK
149
42023ES–SAM–07/2013
ATSAM4L8/L4/L2
2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.
Notations:
C
b
= total capacitance of one bus line in pF
t
clkpb
= period of TWI peripheral bus clock
t
prescaled
= period of TWI internal prescaled clock (see chapters on TWIM and TWIS)
The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW-TWI
)
of TWCK.
9.10.5
JTAG Timing
Figure 9-17. JTAG Interface Signals
JTAG2
JTAG3
JTAG1
JTAG4
JTAG0
TMS/TDI
TCK
TDO
JTAG5
JTAG6
JTAG7
JTAG8
JTAG9
JTAG10
Boundary
Scan Inputs
Boundary
Scan Outputs