Atmel SAM4S Xplained Pro Starter Kit Atmel ATSAM4S-XSTK ATSAM4S-XSTK Data Sheet
Product codes
ATSAM4S-XSTK
696
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The modified architecture is presented below:
Figure 35-4. Fractional Baud Rate Generator
35.7.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in
US_BRGR.
US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the
receive part limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode.
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the
receive part limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
35.7.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Glitch-free
Logic
Modulus
Control
FP
FP
BaudRate
SelectedClock
CD
--------------------------------------
=
B
Di
Fi
------
f
×
=
Table 35-6. Binary and Decimal Values for Di
DI field
0001
0010
0011
0100
0101
0110
1000
1001
Di (decimal)
1
2
4
8
16
32
12
20