Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Data Sheet

 581

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of 
data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.

Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted 
instead of the end of TAG.

This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is 
generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.

0

CONTINUOUS

Continuous, as soon as a word is written in the SSC_THR 
Register (if Transmit is enabled), and immediately after the 
end of transfer of the previous data.

1

RECEIVE

Receive start

2

TF_LOW

Detection of a low level on TF signal

3

TF_HIGH

Detection of a high level on TF signal

4

TF_FALLING

Detection of a falling edge on TF signal

5

TF_RISING

Detection of a rising edge on TF signal

6

TF_LEVEL

Detection of any level change on TF signal

7

TF_EDGE

Detection of any edge on TF signal