Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Data Sheet
Product codes
ATSAM4S-XPLD
875
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and UPDM=1 or 2 in
PWM_SCM register):
PWM_SCM register):
registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the bit
UPDULOCK is written at “1” (in PWM_SCUC register) and the end of the current PWM period, then update
the values for the next period.
UPDULOCK is written at “1” (in PWM_SCUC register) and the end of the current PWM period, then update
the values for the next period.
register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of synchronous
channels (when UPRCNT is equal to UPR in
channels (when UPRCNT is equal to UPR in
(PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period.
Note:
If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times
between two updates, only the last written value is taken into account.
between two updates, only the last written value is taken into account.
Figure 38-17.Synchronized Period, Duty-Cycle and Dead-Times Update
PWM_CPRDUPDx Value
PWM_CPRDx
PWM_CDTYx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
-> End of PWM period and UPDULOCK = 1
User s Writing
PWM_DTUPDx Value
User s Writing
PWM_DTx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
- If UPDM = 0
-> End of PWM period and UPDULOCK = 1
- If UPDM = 1 or 2
-> End of PWM period and end of Update Period
PWM_CDTYUPDx Value
User s Writing