Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

105

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL 
allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more 
clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance, 
while keeping the APBx frequency constant.

There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective. 
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read as 
zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when the new 
clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become unstable or 
hang.

It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding 
bit in the Clock Mask register (APBxMASK - refer to 

 for the 

default state of each of the peripheral clocks. 

Clock 

gate

Clock 

gate

Prescaler

Sleep Controller

Sleep mode

CLK_AHB

Clock 

gate

Clock 

gate

CLK_APBA

Clock 

gate

Clock 

gate

CLK_APBC

Clock 

gate

Clock 

gate

CLK_APBB

APBCDIV

APBBDIV

APBADIV

CLK_PERIPHERAL_AHB_0

CLK_PERIPHERAL_AHB_1

CLK_PERIPHERAL_AHB_n

CLK_PERIPHERAL_APBA_0

CLK_PERIPHERAL_APBA_1

CLK_PERIPHERAL_APBA_n

CLK_PERIPHERAL_APBB_0

CLK_PERIPHERAL_APBB_1

CLK_PERIPHERAL_APBB_n

CLK_PERIPHERAL_APBC_0

CLK_PERIPHERAL_APBC_1

CLK_PERIPHERAL_APBC_n

APBCMASK

APBBMASK

APBAMASK

CPUDIV

AHBMASK

CLK_CPU

GCLK

OSC8M

GCLK_MAIN

BKUPCLK

Clock

gate

 Clock

gate

Clock

gate

Clock

gate

Clock

gate

Clock

gate

Clock

gate

Clock

gate

Clock

gate

Clock 

Failure 

Detector 

CLK_MAIN