Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
339
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit groups (refer to the
Control A register description) will define the physical position of the USART signals in
Control A register description) will define the physical position of the USART signals in
24.5.2 Power Management
The USART can continue to operate in any sleep mode where the selected source clock is running. The USART
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to
24.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB, where x represents the specific SERCOM instance number) can be
enabled and disabled in the Power Manager, and the default state of CLK_SERCOMx_APB can be found in the
Peripheral Clock Masking section in
enabled and disabled in the Power Manager, and the default state of CLK_SERCOMx_APB can be found in the
Peripheral Clock Masking section in
.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured
and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to
and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to
registers will require synchronization between the clock domains. Refer to
details.
24.5.4 DMA
Not applicable.
24.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the USART interrupts requires the Interrupt
Controller to be configured first. Refer to
Controller to be configured first. Refer to
for details.
24.5.6 Events
Not applicable.
24.5.7 Debug Operation
When the CPU is halted in debug mode, the USART continues normal operation. If the USART is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may
result during debugging. The USART can be forced to halt operation during debugging.
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may
result during debugging. The USART can be forced to halt operation during debugging.
for details.
24.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
following registers:
z
Interrupt Flag Status and Clear register (
)
z
)
z
Data register (
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to