Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
357
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.8.5 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x0C
Reset:
0x00
Property:
Write-Protected
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – RXS: Receive Start Interrupt Enable
0: Receive Start interrupt is disabled.
0: Receive Start interrupt is disabled.
1: Receive Start interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
z
Bit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
interrupt.
z
Bit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
interrupt.
z
Bit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register
Empty interrupt.
Empty interrupt.
Bit
7
6
5
4
3
2
1
0
RXS
RXC
TXC
DRE
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0