Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

(CTRLA.CPHA). SCK polarity is selected by the Clock Polarity bit in the Control A register (CTRLA.CPOL). Data bits are 
shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for the data signals to stabilize.

Leading edge is the first clock edge in a clock cycle, while trailing edge is the second clock edge in a clock cycle.

0

0

0

Rising, sample

Falling, setup

1

0

1

Rising, setup

Falling, sample

2

1

0

Falling, sample

Rising, setup

3

1

1

Falling, setup

Rising, sample

Bit 1
Bit 6

LSB
MSB

Mode 0

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

Mode 2

SS

MSB
LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

MSB first (DORD = 0)
LSB first (DORD = 1)

Mode 1

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

Mode 3

SS