Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
370
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
The SPI has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to
For details on clearing interrupt flags, refer to
25.6.5 Events
Not applicable.
25.6.6 Sleep Mode Operation
During master operation, the generic clock will continue to run in idle sleep mode. If the Run In Standby bit in the Control
A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any
interrupt can wake up the device.
A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any
interrupt can wake up the device.
If CTRLA.RUNSTDBY is zero during master operation, GLK_SERCOMx_CORE will be disabled when the ongoing
transaction is finished. Any interrupt can wake up the device.
transaction is finished. Any interrupt can wake up the device.
During slave operation, writing a one to CTRLA.RUNSTDBY will allow the Receive Complete interrupt to wake up the
device.
device.
If CTRLA.RUNSTDBY is zero during slave operation, all reception will be dropped, including the ongoing transaction.
25.6.7 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
synchronized when accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control A register (CTRLA.SWRST)
z
Enable bit in the Control A register (CTRLA.ENABLE)
z
Receiver Enable bit in the Control B register (CTRLB.RXEN)
CTRLB.RXEN behaves somewhat differently than described above. Refer to CTRLB for details.
Write-synchronization is denoted by the Write-Synchronized property in the register description.