Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
393
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Figure 26-5. SCL Timing
The following parameters are timed using the SCL low time period. This comes from the Master Baud Rate Low bit group
in the Baud Rate register (BAUD.BAUDLOW) when non-zero, or the Master Baud Rate bit group in the Baud Rate
register (BAUD.BAUD) when BAUD.BAUDLOW is zero.
in the Baud Rate register (BAUD.BAUDLOW) when non-zero, or the Master Baud Rate bit group in the Baud Rate
register (BAUD.BAUD) when BAUD.BAUDLOW is zero.
z
T
LOW
– Low period of SCL clock
z
T
SU;STO
– Set-up time for stop condition
z
T
BUF
– Bus free time between stop and start conditions
z
T
HD;STA
– Hold time (repeated) start condition
z
T
SU;STA
– Set-up time for repeated start condition
z
T
HIGH
is timed using the SCL high time count from BAUD.BAUD
z
T
RISE
is determined by the bus impedance; for internal pull-ups. Refer to
for details.
z
T
FALL
is determined by the open-drain current limit and bus impedance; can typically be regarded as zero.
for details.
The SCL frequency is given by:
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the
following formula will give the SCL frequency:
following formula will give the SCL frequency:
When BAUD.BAUDLOW is non-zero, the following formula is used to determine the SCL frequency:
T
HD;STA
T
LOW
T
HIGH
T
BUF
T
RISE
SCL
SDA
T
SU;STO
T
SU;STA
P
S
Sr
T
FALL
RISE
HIGH
LOW
SCL
T
T
T
f
+
+
=
1
RISE
GCLK
GCLK
SCL
T
BAUD
f
f
f
+
+
=
)
5
(
2
RISE
GCLK
GCLK
SCL
T
BAUDLOW
BAUD
f
f
f
+
+
+
=
10