Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

writing a 1 to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software’s 
complexity and code size.

The I

2

C slave operates according to the behavior diagram shown in 

. The circles with a capital S followed by 

a number (S1, S2... etc.) indicate which node in the figure the bus logic can jump to based on software or hardware 
interaction.

This diagram is used as reference for the description of the I

2

C slave operation throughout the document. 

When the I

2

C slave is properly configured, it will wait for a start condition to be detected. When a start condition is 

detected, the successive address packet will be received and checked by the address match logic. If the received 
address is not a match, the packet is rejected and the I

2

C slave waits for a new start condition. The I

2

C slave Address 

Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set when a start condition followed by a valid address 
packet is detected. SCL will be stretched until the I

2

C slave clears INTFLAG.AMATCH. Because the I

2

C slave holds the 

clock by forcing SCL low, the software is given unlimited time to respond to the address.

The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register 
(STATUS.DIR), and the bit will be updated only when a valid address packet is received.

If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to 
the I

2

C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to 

software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are 
intended to follow the SMBus Address Resolution Protocol (ARP).

After the address packet has been received from the I

2

C master, one of two cases will arise based on transfer direction.

The STATUS.DIR bit is one, indicating an I

2

C master read operation. The SCL line is forced low, stretching the bus clock. 

If an ACK is sent, I

2

C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), 

Interrupt on STOP 
Condition Enabled

Software interaction

The master provides data 
on the bus

Addressed slave provides 
data on the bus