Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a 
command is given. 

This bit is not enable-protected.

z

Bits 15:14 – AMODE[1:0]: Address Mode
These bits set the addressing mode according to 

.

Note:

1.

See 

 for additional information.

These bits are not write-synchronized.

z

Bits 13:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.

z

Bit 8 – SMEN: Smart Mode Enable
This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is 
read.

0: Smart mode is disabled.

1: Smart mode is enabled.

This bit is not write-synchronized.

0x0

X

(No action)

0x1

X

(Reserved)

0x2

Used to complete a transaction in response to a data interrupt (DRDY)

0 (Master write)

Execute acknowledge action succeeded by waiting for any start (S/Sr) condition

1 (Master read)

Wait for any start (S/Sr) condition

0x3

Used in response to an address interrupt (AMATCH)

0 (Master write)

Execute acknowledge action succeeded by reception of next byte

1 (Master read)

Execute acknowledge action succeeded by slave data interrupt

Used in response to a data interrupt (DRDY)

0 (Master write)

Execute acknowledge action succeeded by reception of next byte

1 (Master read)

Execute a byte read operation followed by ACK/NACK reception

0x0

MASK

The slave responds to the address written in ADDR.ADDR masked by the value in 
ADDR.ADDRMASK

(1)

.

0x1

2_ADDRS

The slave responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.

0x2

RANGE

The slave responds to the range of addresses between and including ADDR.ADDR and 
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.

0x3

-

Reserved.