Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

INTFLAG

0x0E

0x00

-

z

Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.

z

Bit 2 – DRDY: Data Ready
This flag is set when a I

2

C slave byte transmission is successfully completed. 

The flag is cleared by hardware when either:

z

Writing to the DATA register.

z

Reading the DATA register with smart mode enabled.

z

Writing a valid command to the CMD register.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Data Ready interrupt flag. Optionally, the flag can be cleared manually by writ-
ing a one to INTFLAG.DRDY.

z

Bit 1 – AMATCH: Address Match
This flag is set when the I

2

C slave address match logic detects that a valid address has been received. 

The flag is cleared by hardware when CTRL.CMD is written. 

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Address Match interrupt flag. Optionally the flag can be cleared manually by 
writing a one to INTFLAG.AMATCH. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT.

z

Bit 0 – PREC: Stop Received
This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected 
between a bus master and another slave will not set this flag. 

This flag is cleared by hardware after a command is issued on the next address match.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Stop Received interrupt flag. Optionally, the flag can be cleared manually by 
writing a one to INTFLAG.PREC. 

Bit

7

6

5

4

3

2

1

0

Access

R

R

R

R

R

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0