Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
42
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Some features not activated by APB transactions are not available when the device is protected:
12.10 Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified
as an ATMEL device implementing a DSU. The DSU contains identification registers to differentiate the device.
as an ATMEL device implementing a DSU. The DSU contains identification registers to differentiate the device.
12.10.1 CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM
implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM
implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
Figure 12-5. Conceptual 64-Bit Peripheral ID
Figure 12-4. APB Memory Mapping
0x0000
DSU operating
registers
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
0x00FC
0x0100
Replicated
DSU operating
registers
External address range
(can be accessed from debug tools with some restrictions)
(can be accessed from debug tools with some restrictions)
0x01FD
Empty
0x1000
DSU CoreSight
ROM
0x1FFC
Table 12-1. Feature Availability Under Protection
Features
Availability When the Device is Protected
CPU reset extension
Yes
Debugger Cold-Plugging
Yes
Debugger Hot-Plugging
No