Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the TC is reset. See the 

The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to 
determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be 
generated. Refer to 

 for details.

The TC can generate the following output events:

z

Overflow/Underflow (OVF)

z

Match or Capture (MC)

Writing a one to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output 
event. Writing a zero to this bit disables the corresponding output event. 

To enable one of the following event actions, write to the Event Action bit group (EVCTRL.EVACT).

z

Start the counter 

z

Retrigger counter 

z

Increment or decrement counter (depends on counter direction) 

z

Capture event 

z

Capture period 

z

Capture pulse width 

Writing a one to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC. 
Writing a zero to this bit disables input events to the TC. Refer to 

 for details on 

configuring the Event System.

The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the Control 
A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep 
mode or perform actions through the Event System.

Due to the asynchronicity between CLK_TCx_APB and GCLK_TCx some registers must be synchronized when 
accessed. A register can require:

z

Synchronization when written

z

Synchronization when read

z

Synchronization when written and read

z

No synchronization

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status 
register(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The 
synchronization Ready interrupt can be used to signal when sync is complete. This can be accessed via the 
Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).

If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All 
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is 
stalled.

The following bits need synchronization when written:

z

Software Reset bit in the Control A register (CTRLA.SWRST)

z

Enable bit in the Control A register (CTRLA.ENABLE)