Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
488
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
28.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to
the Write-Protected property in each individual register description. Refer to
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to
or the Read-Synchronized property in each individual register description. Refer to
for
details.
Some registers are enable-protected, meaning they can be written only when the ADC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
denoted by the Enable-Protected property in each individual register description.
28.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00
Property:
Write-Protected
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RUNSTDBY: Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
This bit indicates whether the ADC will continue running in standby sleep mode or not:
0: The ADC is halted during standby sleep mode.
1: The ADC continues normal operation during standby sleep mode.
z
Bit 1 – ENABLE: Enable
0: The ADC is disabled.
0: The ADC is disabled.
1: The ADC is enabled.
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
disabled.
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
ENABLE
SWRST
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0