Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
520
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Figure 29-5. VDDANA Scaler
29.6.7 Input Hysteresis
Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help prevent
constant toggling of the output, which can be caused by noise when the input signals are close to each other. Hysteresis
is enabled for each comparator individually by the Hysteresis Mode bit in the Comparator x Control register
(COMPCTRLx.HYST). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0).
constant toggling of the output, which can be caused by noise when the input signals are close to each other. Hysteresis
is enabled for each comparator individually by the Hysteresis Mode bit in the Comparator x Control register
(COMPCTRLx.HYST). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0).
29.6.8 Propagation Delay vs. Power Consumption
It is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or the
lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit group in
the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current provided to
the comparator, and as such will also affect the start-up time.
lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit group in
the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current provided to
the comparator, and as such will also affect the start-up time.
29.6.9 Filtering
The output of the comparators can be digitally filtered to reduce noise using a simple digital filter. The filtering is
determined by the Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for
each comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in
the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the
CLK_AC frequency scaled by the prescaler setting in the Control A register (CTRLA.PRESCALER).
determined by the Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for
each comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in
the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the
CLK_AC frequency scaled by the prescaler setting in the Control A register (CTRLA.PRESCALER).
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the
comparator output is validated. For continuous mode, the first valid output will occur when the required number of filter
samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the previous N-1
samples, as shown in
comparator output is validated. For continuous mode, the first valid output will occur when the required number of filter
samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the previous N-1
samples, as shown in
. For single-shot mode, the comparison completes after the Nth filter sample, as shown
in
.
COMPCTRLx.MUXNEG
== 5
SCALERx.
VALUE
to
COMPx
COMPx
6