Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
624
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
35.2.6 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
(XOSC32K.AAMPEN = 0)
35.2.7 DFLL48M
1 - If the firmware writes to the DFLLMUL.MUL register in the same cycle as
the closed loop mode tries to update it, the fine calibration will first be reset
to midpoint and then incremented/decremented by the closed loop mode.
Then the coarse calibration will be performed with the updated fine value. If
this happens before the dfll have got a lock, the new fine calibration value
can be anything between 128-DFLLMUL.FSTEP and 128+DFLLMUL.FSTEP
which could give smaller calibration range for the fine calibration. Errata
reference: 10634
the closed loop mode tries to update it, the fine calibration will first be reset
to midpoint and then incremented/decremented by the closed loop mode.
Then the coarse calibration will be performed with the updated fine value. If
this happens before the dfll have got a lock, the new fine calibration value
can be anything between 128-DFLLMUL.FSTEP and 128+DFLLMUL.FSTEP
which could give smaller calibration range for the fine calibration. Errata
reference: 10634
Fix/Workaround:
Always wait until the DFLL48M has locked before writing the DFLLMUL.MUL
register
register
2 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
configuring the DFLL module.
3 - Changing the DFLLVAL.FINE calibration bits of the DFLL48M Digital
Frequency Locked Loop might result in a short output frequency overshoot.
This might occur both in open loop mode while writing DFLLVAL.FINE by
software and closed loop mode when the DFLL automatically adjusts its
output frequency. Errata reference: 10537
Frequency Locked Loop might result in a short output frequency overshoot.
This might occur both in open loop mode while writing DFLLVAL.FINE by
software and closed loop mode when the DFLL automatically adjusts its
output frequency. Errata reference: 10537
Fix/Workaround:
- When using DFLL48M in open loop mode, be sure the DFLL48M is not used by
any module while DFLLVAL.FINE is written.
any module while DFLLVAL.FINE is written.
- When using DFLL48M in closed loop mode, be sure that DFLLCTRL.STABLE is
written to 1. The DFLL clock should not be used by any modules until the DFLL
locks are set.
written to 1. The DFLL clock should not be used by any modules until the DFLL
locks are set.
If the application requires on-the-fly DFLL calibration (temperature/VCC drift
compensation), the firmware should perform, either periodically or when the
DFLL48M frequency differ too much from target frequency (indicated by
DFLLVAL.DIFF), the following:
compensation), the firmware should perform, either periodically or when the
DFLL48M frequency differ too much from target frequency (indicated by
DFLLVAL.DIFF), the following:
o Switch system clock/module clocks to different clock than DFLL48M
o Re-initiate a DFLL48M closed loop lock sequence by disabling and re-enabling
the DFLL48M
the DFLL48M