Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
628
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
4 - The PORT output driver strength feature is not available. Errata
reference: 12684
reference: 12684
Fix/Workaround:
None
5 - Maximum toggle frequency on all pins in worst case operating condition
is 8MHz. This affects all operations on the pins, including serial
communications. Errata reference: 10335
is 8MHz. This affects all operations on the pins, including serial
communications. Errata reference: 10335
Fix/Workaround:
None.
6 - Do not enable Timers/Counters, AC (Analog Comparator), GCLK (Generic
Clock Controller), and SERCOM (I2C and SPI) to control Digital outputs in
standby sleep mode. Errata reference: 12786
Clock Controller), and SERCOM (I2C and SPI) to control Digital outputs in
standby sleep mode. Errata reference: 12786
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode.
This is done by setting the RUNSTDBY bit in the VREG register.
This is done by setting the RUNSTDBY bit in the VREG register.
7 - After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD is
cleared while the clock is still broken, the system is stuck. Errata reference:
12687
cleared while the clock is still broken, the system is stuck. Errata reference:
12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a system
reset.
reset.
8 - The temperature sensor is not accurate. No value is written into the
Temperature Log row during production test. Errata reference: 11731
Temperature Log row during production test. Errata reference: 11731
Fix/Workaround:
None
9 - The DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and
DFLLMUL.FSTEP bit groups are not correctly located in the register map.
DFLLVAL.COARSE is only 5 bits and located in DFLLVAL[12..8].
DFLLVAL.FINE is only 8 bits and located in DFLLVAL[7:0]. DFLLMUL.CSTEP
is only 5 bits and located in DFLLMUL[28:24]. DFLLMUL.FSTEP is only 8 bits
and located in DFLLMUL[23:16] Errata reference: 10988
DFLLMUL.FSTEP bit groups are not correctly located in the register map.
DFLLVAL.COARSE is only 5 bits and located in DFLLVAL[12..8].
DFLLVAL.FINE is only 8 bits and located in DFLLVAL[7:0]. DFLLMUL.CSTEP
is only 5 bits and located in DFLLMUL[28:24]. DFLLMUL.FSTEP is only 8 bits
and located in DFLLMUL[23:16] Errata reference: 10988
Fix/Workaround:
DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and DFLLMUL.FSTEP
should not be used if code compatibility is required with future device revisions.
should not be used if code compatibility is required with future device revisions.