Linear Technology DC1190A-B - LTC2365: 12-bit, 1Msps SAR ADC (req DC590B for DC apps, DC890B for AC apps) DC1190A-B DC1190A-B Data Sheet
Product codes
DC1190A-B
LTC2365/LTC2366
5
23656fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When this pin, A
Note 2: All voltage values are with respect to GND.
Note 3: When this pin, A
IN
, is taken below GND or above V
DD
, it will be
clamped by internal diodes. These products can handle input currents
greater than 100mA below GND or above V
DD
without latchup.
Note 4: V
DD
= OV
DD
= V
REF
= 2.35V to 3.6V, f
SMPL
= f
SMPL(MAX)
and
f
SCK
= f
SCK(MAX)
unless otherwise specified.
Note 5: Integral linearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Linearity, offset and gain specifications apply for a single-ended
A
IN
input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specified with
Note 8: Guaranteed by characterization. All input signals are specified with
t
r
= t
f
= 2ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: Minimum f
Note 10: Minimum f
SCK
at which specifications are guaranteed.
Note 11: The time required for the output to cross the V
IH
or V
IL
voltage.
Note 12: Guaranteed by design, not subject to test.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
SYMBOL
PARAMETER
CONDITIONS
LTC2365
LTC2366
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
f
SMPL(MAX)
Maximum Sampling Frequency
(Notes 8, 9)
l
1
3
MHz
f
SCK
Shift Clock Frequency
(Notes 8, 9, 10)
l
0.5
16
0.5
48
MHz
t
SCK
Shift Clock Period
l
62.5
2000
20.8
2000
ns
t
THROUGHPUT
Minimum Throughput Time, t
ACQ
+ t
CONV
l
1000
333
ns
t
ACQ
Acquisition Time
l
181.5
56
ns
t
CONV
Conversion Time
l
818.5
277
ns
t
QUIET
SDO Hi-Z State to CS
↓
(Notes 8, 9)
l
4
4
ns
t
1
Minimum Positive or Negative CS Pulse Width (Notes 8)
l
4
4
ns
t
2
SCK
↓ Setup Time After CS↓
(Notes 8)
l
6
2000
6
2000
ns
t
3
SDO Enabled Time After CS
↓
(Notes 9, 11, 12)
l
4
4
ns
t
4
SDO Data Valid Access Time After SCK
↓
(Notes 8, 9, 11)
l
15
15
ns
t
5
SCK LOW Time
l
40%
40%
t
SCK
t
6
SCK HIGH Time
l
40%
40%
t
SCK
t
7
SDO Data Valid Hold Time After SCK
↓
(Notes 8, 9, 11)
l
5
5
ns
t
8
SDO into Hi-Z State Time After SCK
↓
(Notes 9, 12)
l
5
30
5
14
ns
t
9
SDO into Hi-Z State Time After CS
↑
(Notes 9, 12)
l
4.2
4.2
ns
t
POWER-UP
Power-Up Time from Sleep Mode
See Sleep Mode section
l
1000
333
ns
tiMing characteristics
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 4)