Linear Technology DC1190A-B - LTC2365: 12-bit, 1Msps SAR ADC (req DC590B for DC apps, DC890B for AC apps) DC1190A-B DC1190A-B Data Sheet
Product codes
DC1190A-B
LTC2365/LTC2366
9
23656fb
pin Functions
LTC2365/LTC2366 (S6 Package)
V
V
DD
(Pin 1): Positive Supply. The V
DD
range is 2.35V to
3.6V. V
DD
also defines the input span of the ADC, 0V to
V
DD
. Bypass to GND and to a solid ground plane with a
10µF ceramic capacitor (or 10µF tantalum in parallel with
0.1µF ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
A
A
IN
(Pin 3): Analog Input. A
IN
is a single-ended input with
respect to GND with a range from 0V to V
DD
.
SCK (Pin 4): Shift Clock Input. The SCK serial clock ad-
vances the conversion process. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
CS (Pin 6): Chip Select Input. This active low signal starts
CS (Pin 6): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.
LTC2365/LTC2366 (TS8 Package)
V
V
DD
(Pin 1): Positive Supply. The V
DD
range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
10µF ceramic capacitor (or 10µF tantalum in parallel with
0.1µF ceramic).
V
V
REF
(Pin 2): Reference Input. V
REF
defines the input
span of the ADC, 0V to V
REF
and the V
REF
range is 1.4V
to V
DD
. Bypass to GND and to a solid ground plane with
a 4.7µF ceramic capacitor (or 4.7µF tantalum in parallel
with 0.1µF ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
A
A
IN
(Pin 4): Analog Input. A
IN
is a single-ended input with
respect to GND with a range from 0V to V
REF
.
OV
DD
(Pin 5): Output Driver Supply for SDO. The OV
DD
range is 1V to V
DD
. Bypass to GND and to a solid ground
plane with a 4.7µF ceramic capacitor (or 4.7µF tantalum
in parallel with 0.1µF ceramic).
SDO (Pin 6): Three-State Serial Data Output. The A/D
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock ad-
SCK (Pin 7): Shift Clock Input. The SCK serial clock ad-
vances the conversion process. SDO data transitions on
the falling edge of SCK.
CS (Pin 8): Chip Select Input. This active low signal starts
CS (Pin 8): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.