Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.

 shows a read access controlled by NRD, followed by a write access

controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:

NRDHOLD = 4; READMODE = 1 (NRD controlled)

NWESETUP = 3; WRITEMODE = 1 (NWE controlled)

TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).

Figure 15-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins

When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.

 and 

the cases:

• read access followed by a read access on another chip select.

• read access followed by a write access on another chip select.

CLK_SMC

A[AD_MSB:2]

NRD

NWE

NCS0

D[15:0]

Read access on NCS0 (NRD controlled)

Read to Write

Wait State

Write access on NCS0 (NWE controlled)

TDFCYCLES = 6

NWESETUP = 3

NRDHOLD = 4