Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

This field is used only if DBW defines a 16-bit data bus.

The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the 

read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for 

the read and write controlling signal.

1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be 

inserted after the setup of NWE.

0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be 

inserted after the setup of NCS.

0

8-bit  bus

1

16-bit  bus

2

Reserved

3

Reserved

0

Byte select access type:

Write operation is controlled using NCS, NWE, NBS0, NBS1

Read operation is controlled using NCS, NRD, NBS0, NBS1

1

Byte write access type:

Write operation is controlled using NCS, NWR0, NWR1

Read operation is controlled using NCS and NRD

0

Disabled:

the NWAIT input signal is ignored on the corresponding chip select.

1

Reserved

2

Frozen Mode:

if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle 
is resumed from the point where it was stopped.

3

Ready Mode:

the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read 
or write signal, to complete the access. If high, the access normally completes. If low, the access is extended 
until NWAIT returns high.