Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
236
32072H–AVR32–10/2012
AT32UC3A3
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
• NB: Number of Banks
Reset value is two banks.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NC: Number of Column Bits
Reset value is 8 column bits.
CAS
CAS Latency (Cycles)
0
Reserved
1
1
2
2
3
3
NB
Number of Banks
0
2
1
4
NR
Row Bits
0
11
1
12
2
13
3
Reserved
NC
Column Bits
0
8
1
9
2
10
3
11