Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
300
32072H–AVR32–10/2012
AT32UC3A3
18.7.17
Performance Control Register
Name:
PCONTROL
Access Type:
Read/Write
Offset:
0x800
Reset Value:
0x00000000
• MON1CH: Performance Monitor Channel 1
• MON0CH: Performance Monitor Channel 0
• MON0CH: Performance Monitor Channel 0
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
• CH1RES: Performance Channel 1 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON1CH.
This bit always reads as zero.
• CH0RES: Performance Channel 0 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON0CH.
This bit always reads as zero.
• CH1OF: Channel 1 Overflow Freeze
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1OF: Channel 0 Overflow Freeze
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1EN: Performance Channel 1 Enable
0: Performance channel 1 is disabled.
1: Performance channel 1 is enabled.
• CH0EN: Performance Channel 0 Enable
0: Performance channel 0 is disabled.
1: Performance channel 0 is enabled.
31
30
29
28
27
26
25
24
-
-
MON1CH
23
22
21
20
19
18
17
16
-
-
MON0CH
15
14
13
12
11
10
9
8
-
-
-
-
-
-
CH1RES
CH0RES
7
6
5
4
3
2
1
0
-
- CH1OF
CH0OF
-
-
CH1EN
CH0EN