Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
314
32072H–AVR32–10/2012
AT32UC3A3
18.8
Module Configuration
The specific configuration for the PDCA instance is listed in the following tables.
18.8.1
DMA Handshake Signals
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 18-6.
PDCA Configuration
Features
PDCA
Number of channels
8
Table 18-7.
Register Reset Values
Register
Reset Value
PSRn
n
VERSION
0x00000110
Table 18-8.
PDCA Handshake Signals
PID Value
Direction
Peripheral Instance
Peripheral Register
0
RX
ADC CDRx
1
RX
SSC
RHR
2
RX
USART0
RHR
3
RX
USART1
RHR
4
RX
USART2
RHR
5
RX
USART3
RHR
6
RX
TWIM0
RHR
7
RX
TWIM1
RHR
8
RX
TWIS0
RHR
9
RX
TWIS1
RHR
10
RX
SPI0
RDR
11
RX
SPI1
RDR
12
TX
SSC
THR
13
TX
USART0
THR
14
TX
USART1
THR
15
TX
USART2
THR
16
TX
USART3
THR
17
TX
TWIM0
THR
18
TX
TWIM1
THR
19
TX
TWIS0
THR
20
TX
TWIS1
THR