Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
407
32072H–AVR32–10/2012
AT32UC3A3
21.7.2
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
shows the four modes and corresponding parameter settings.
and
show examples of data transfers.
Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Table 21-2.
SPI modes
SPI Mode
CPOL
NCPHA
0
0
1
1
0
0
2
1
1
3
1
0
1
4
3
2
5
8
7
6
SPCK cycle (for reference)
SPCK
(CPOL = 0)
NSS
(to slave)
MISO
(from slave)
MOSI
(from master)
SPCK
(CPOL = 1)
MSB
6
4
5
LSB
1
2
3
MSB
6
***
LSB
1
2
3
4
5
*** Not Defined, but normaly MSB of previous character received