Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The power level of the internal voltage regulator is also adjusted according to the sleep mode to
reduce the internal regulator power consumption.

Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.

Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.

The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.

When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete,
the CPU should perform a read operation from any register on the PB bus before executing the
sleep instruction. This will stall the CPU while waiting for any pending PB operations to
complete.

When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt
should be disabled (USBCON.VBUSTE = 0).

The USB can be used to wake up the part from sleep modes through register AWEN of the
Power Manager.

Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined number of generic clocks that can provide a wide range of accurate clock frequencies.

Sleep Modes