Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

CSR.RXRDY bits to trigger one byte writes or reads. It always writes to THR, and it always reads
RHR.

The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration:

• LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write 

buffer.

• LINMR.PDCM=1: LIN configuration is written by the Peripheral DMA Controller to THR, and 

is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two 
accesses. The first writes the NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits in the 
LINMR register, while the second writes the LINMR.DLC field. If LINMR.NACT=PUBLISH, 
the write buffer will also contain the Identifier.

When LINMR.NACT=SUBSCRIBE, the read buffer contains the data.

Figure 25-39. Master Node with Peripheral DMA Controller (LINMR.PDCM=0)

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RXRDY

TXRDY

Peripheral 

bus

USART LIN 

CONTROLLER

DATA 0

DATA N

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READ BUFFER

NODE ACTION = PUBLISH

NODE ACTION = SUBSCRIBE

Peripheral DMA 

Controller

RXRDY

Peripheral 

bus

DATA 0

DATA 1

DATA N

WRITE BUFFER

Peripheral DMA 

Controller

USART LIN 

CONTROLLER