Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
647
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-18. Abort Algorithm
27.7.2.13
Management of OUT endpoints
•Overview
OUT packets are sent by the host. All the data can be read which acknowledges or not the bank
when it is empty.
when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers
an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is
one.
an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is
one.
RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO.
(RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO (see
) and clears the FIFOCON bit to free the bank. If the OUT endpoint is
composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON
bits are updated in accordance with the status of the next bank.
bits are updated in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not empty, i.e. the software can read further data
from the FIFO.
from the FIFO.
Endpoint
Abort
Abort Done
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
that no bank is busy, i.e.,
that nothing has to be sent
Disable the TXINI interrupt.
EPRSTn = 1
NBUSYBK
== 0?
Yes
TXINEC = 1
No
KILLBKS = 1
KILLBK
== 1?
Yes
Kill the last written bank.
Wait for the end of the
procedure
procedure
No