Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-
CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data
Interrupt Enable (TXOUTE) bit in UPCONn is one.

TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the
pipe FIFO.

The user then writes into the FIFO (see 

) and clears the FIFOCON bit to allow the USBB to send the data. If the

OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.

TXOUTI shall always be cleared before clearing FIFOCON.

The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.

Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.

Note that in High-Speed operating mode, the host controller automatically manages the PING
protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the
Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction
(BINTERVALL) field in UPCFGn. See the 

 for more details.

Figure 27-26. Example of an OUT Pipe with one Data Bank

OUT

DATA

(bank 0)

ACK

TXOUTI

FIFOCON

HW

write data to CPU

BANK 0

SW

SW

SW

SW

OUT

write data to CPU

BANK 0