Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if 

STOE is one.

This bit is cleared when the UBSTACLR.STOIC bit is written to one.

This bit shall only be used in host mode.

This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host). 

This triggers a USB interrupt if ROLEEXE is one.

This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one.

This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one.

This bit is cleared when the UBSTACLR.BCERRIC bit is written to one.

This bit shall only be used in host mode.

This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one.

This bit is cleared when the UBSTACLR.VBERRIC bit is written to one.

This bit shall only be used in host mode.

If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of 

VBUSHWC is one.

This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB 

interrupt if VBUSTE is one.

This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB 

interrupt if IDTE is one.

This bit is cleared when the UBSTACLR.IDTIC bit is written to one.

This interrupt is generated even if the clock is frozen by the FRZCLK bit or pad is disable by USBCON.OTGPADE or the USBB 

module is disabled by USBCON.USBE.