Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then 

automatically sent by the USBB.

An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not 

fast enough. The packet is lost.

Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.

This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.

This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT 

interrupt if RXSTPE is one.

Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.

This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints.

This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an 

EPnINT interrupt if RXOUTE is one.

Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the 

bank.

This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. 

This triggers an EPnINT interrupt if RXOUTE is one.

Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge 

the interrupt, what has no effect on the endpoint FIFO.

The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple 

banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the 

next bank.

RXOUTI shall always be cleared before clearing FIFOCON.

This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.

This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt 

if TXINE is one.

This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.

This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free. 

This triggers an EPnINT interrupt if TXINE is one.

This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint 

FIFO.

The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is 

composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance 

with the status of the next bank.

TXINI shall always be cleared before clearing FIFOCON.

This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.