Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
71
32072H–AVR32–10/2012
AT32UC3A3
7.6.13
Generic Clock Control Register
Name: GCCTRLx
Access Type:
Read/Write
Offset:
0x60 - 0x74
Reset Value:
0x00000000
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
• DIVEN: Divide Enable
• DIVEN: Divide Enable
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
• CEN: Clock Enable
0: Clock is stopped.
1: Clock is running.
• PLLSEL: PLL Select
0: Oscillator is source for the generic clock.
1: PLL is source for the generic clock.
• OSCSEL: Oscillator Select
0: Oscillator (or PLL) 0 is source for the generic clock.
1: Oscillator (or PLL) 1 is source for the generic clock.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
DIV[7:0]
7
6
5
4
3
2
1
0
-
-
-
DIVEN
-
CEN
PLLSEL
OSCSEL