Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes

AT32UC3A3-XPLD

738

32072H–AVR32–10/2012

AT32UC3A3

• RXSTALLDE: Received STALLed Interrupt Enable

This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE).

This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt

(RXSTALLDE).

• CRCERRE: CRC Error Interrupt Enable

This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).

This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE).

• OVERFIE: Overflow Interrupt Enable

This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE).

This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE).

• NAKEDE: NAKed Interrupt Enable

This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE).

This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE).

• PERRE: Pipe Error Interrupt Enable

This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE).

This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE).

• TXSTPE: Transmitted SETUP Interrupt Enable

This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE).

This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE).

• UNDERFIE: Underflow Interrupt Enable

This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE).

This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UNDERFIE).

• TXOUTE: Transmitted OUT Data Interrupt Enable

This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE).

This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE).

• RXINE: Received IN Data Interrupt Enable

This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE).

This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE).