Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.

In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE). 

The OVREn and GOVRE bits are automatically cleared when the SR register is read.

Figure 29-3. GOVRE and OVREn Flag Behavior 

Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and 

its 

corresponding EOC and OVRE

flags in SR are unpredictable.

Read SR

Data C

Data C

Data B

Data B

Data A

Data A

Undefined Data

Undefined Data

Undefined Data

LCDR

CRD0

CH1(CHSR)

CH0(CHSR)

TRIGGER

CRD1

EOC0(SR)

EOC1(SR)

GOVRE(SR)

DRDY(ASR)

OVRE0(SR)

Read CDR0

Read CDR1

Conversion

Conversion

Conversion