Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

• When MR.LOD is zero 

The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read.

Figure 33-1. Manual and Automatic Modes when MR.LOD is zero

If the user does not want to read the output data registers between each encryption/decryption,
the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot
know the end of the following encryptions/decryptions.

• When MR.LOD is one

The ISR.DATRDY bit is cleared when at least one IDATAnR register is written, so before the
start of a new transfer. No more ODATAnR register reads are necessary between consecutive
encryptions/decryptions.

Figure 33-2. Manual and Automatic Modes when MR.LOD is one

• when MR.LOD is zero

The end of the encryption/decryption should be monitored with the DMA Controller.

Write CR.START (Manual mode)

Or

Write IDATAnR register(s) (Auto mode)

ISR.DATRDY

Encryption or Decryption Process

Read ODATAnR register(s)

Write IDATAnR register(s)

Encryption or Decryption Process

Write CR.START(Manual mode)

or

Write IDATAnR register(s) (Auto mode)

ISR.DATRDY