Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes
AT32UC3A3-XPLD
Page of 1021
943
32072H–AVR32–10/2012
AT32UC3A3
35.5
JTAG Instruction Summary
The implemented JTAG instructions in the 32-bit AVR are shown in the table below.
35.5.1
Security Restrictions
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
Table 35-7.
JTAG Instruction Summary
Instruction 
OPCODE
Instruction
Description
0x01
IDCODE
Select the 32-bit Device Identification register as data register.
0x02
SAMPLE_PRELOAD
Take a snapshot of external pin values without affecting system operation.
0x03
EXTEST
Select boundary-scan chain as data register for testing circuitry external to 
the device.
0x04
INTEST
Select boundary-scan chain for internal testing of the device.
0x06
CLAMP
Bypass device through Bypass register, while driving outputs from boundary-
scan register. 
0x0C
AVR_RESET
Apply or remove a static reset to the device
0x0F
CHIP_ERASE
Erase the device
0x10
NEXUS_ACCESS
Select the SAB Address and Data registers as data register for the TAP. The 
registers are accessed in Nexus mode.
0x11
MEMORY_WORD_ACCESS
Select the SAB Address and Data registers as data register for the TAP.
0x12
MEMORY_BLOCK_ACCESS
Select the SAB Data register as data register for the TAP. The address is 
auto-incremented.
0x13
CANCEL_ACCESS
Cancel an ongoing Nexus or Memory access.
0x14
MEMORY_SERVICE
Select the SAB Address and Data registers as data register for the TAP. The 
registers are accessed in Memory Service mode.
0x15
MEMORY_SIZED_ACCESS
Select the SAB Address and Data registers as data register for the TAP.
0x17
SYNC
Synchronization counter
0x1C
HALT
Halt the CPU for safe programming.
0x1F
BYPASS
Bypass this device through the bypass register.
Others
N/A
Acts as BYPASS